1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to P-channel transistors comprising a high-k metal gate electrode formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element in complex integrated circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity, in combination with a desired channel controllability.
With a reduced channel length, generally, a shallow dopant profile may be required in the drain and source regions, while, nevertheless, a moderately high dopant concentration is required in view of providing a low series resistance, which in turn results in a desired drive current in combination with a reduced transistor channel. A shallow dopant profile in combination with a low overall drain and source resistance is typically realized by forming so-called drain and source extension regions, which may represent extremely shallow doped areas extending below the gate electrode structure so as to appropriately connect to the channel region. On the other hand, an increased lateral offset from the channel region is adjusted on the basis of appropriately dimensioned sidewall spacers, which are used as implantation masks for forming the actual drain and source regions with a desired high dopant concentration and with an increased depth compared to the drain and source extension regions. By appropriately selecting the size of the drain and source extension regions, channel controllability may be maintained for very short channel transistors while also providing a desired low overall series resistance in connecting the drain and source regions to the channel region. Consequently, for a desired performance of sophisticated transistor elements, a certain degree of overlap of the drain and source extension regions with the gate electrode is desirable in order to obtain a low threshold voltage and a high current drive capability. The overlap of the drain and source extension regions with the gate electrode gives rise to a specific capacitive coupling that is also referred to as Miller capacitance. Typically, a desired Miller capacitance is adjusted on the basis of implantation processes in which the drain and source dopants may be introduced in order to form the basic configuration of the drain and source extension regions, wherein the final shape of these regions may then be adjusted on the basis of a sequence of anneal processes in which implantation-induced damages are re-crystallized and also a certain degree of dopant diffusion may occur, thereby finally determining the resulting Miller capacitance.
Upon continuously reducing the channel length of field effect transistors, generally, an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may become increasingly incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in increasing the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors. One promising approach in this respect is the generation of a certain type of strain in the channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors. The desired compressive strain component may be obtained according to well-established approaches by incorporating a strain-inducing semiconductor material, for instance in the form of a silicon/germanium mixture or alloy, in the active region of the P-channel transistor. For example, after forming the gate electrode structure, corresponding cavities may be formed laterally adjacent to the gate electrode structure in the active region and may be refilled with the silicon/germanium alloy which, when grown on the silicon material, may have an internal strained state, which in turn may induce a corresponding compressive strain component in the adjacent channel region. Consequently, a plurality of process strategies have been developed in the past in order to incorporate a highly strained silicon/germanium material in the drain and source areas of P-channel transistors, which may, however, also require corresponding adaptations in view of obtaining a desired lateral and vertical dopant profile for the drain and source regions and the corresponding extension regions as, for instance, boron, which is frequently used as a P-type dopant species, may have a significantly different diffusion behavior in a silicon/germanium material compared to a silicon-based material. That is, in a silicon/germanium material having a germanium concentration of approximately 20 atomic percent or higher, the diffusivity of the boron species is significantly less compared to a silicon, which may have to be taken into consideration when adjusting the overall transistor characteristics. For example, typically, the drain and source extension regions may be formed so as to be located within a silicon material so that the Miller capacitance may be adjusted on the basis of the diffusion characteristics in silicon material to obtain the required overlap of the drain and source extension regions with the gate electrode structure without having to take into consideration the reduced diffusivity in a silicon/germanium material.
During the continuous reduction of the critical dimensions of transistors, an appropriate adaptation of the material composition of the gate dielectric material has been proposed such that, for a physically appropriate thickness of a gate dielectric material, i.e., for reducing the gate leakage currents, nevertheless, a desired high capacitive coupling may be achieved. Thus, material systems have been developed which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials, silicon oxynitride materials and the like. For example, materials including hathium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are, therefore, referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques. As is well known, the electronic characteristics of the transistor elements also strongly depend on the work function of the gate electrode material which influences the band structure of the semiconductor material in the channel region separated from the gate electrode material by the gate dielectric material. In well-established polysilicon/silicon dioxide-based gate electrode structures, the corresponding threshold voltage, strongly influenced by the gate dielectric material and the adjacent electrode material, is adjusted by appropriately doping the polysilicon material in order to appropriately adjust the work function of the polysilicon material at the interface between the gate dielectric material and the electrode material. Similarly, in gate electrode structures including a high-k gate dielectric material, the work function has to be appropriately adjusted for N-channel transistors and P-channel transistors, respectively, which may require appropriately selected work function adjusting metal species, such as lanthanum for N-channel transistors and aluminum for P-channel transistors. For this reason, corresponding metal-containing conductive materials may be positioned close to the high-k gate dielectric material in order to form an appropriately designed interface that results in the target work function of the gate electrode structure. In many conventional approaches, the work function adjustment may be performed at a very late manufacturing stage, i.e., after any high temperature processes, which may require the replacement of a placeholder material of the gate electrode structures, such as polysilicon, and the incorporation of appropriate work function adjusting species in combination with an electrode metal, such as aluminum and the like. In this case, however, very complex patterning and deposition process sequences may be required on the basis of gate electrode structures having critical dimensions of 50 nm and significantly less, which may result in severe variations of the resulting transistor characteristics.
Therefore, other process strategies have been proposed in which the work function adjusting materials may be applied in an early manufacturing stage, i.e., upon forming the gate electrode structures, wherein the corresponding metal species may be thermally stabilized and encapsulated in order to obtain the desired work function and thus threshold voltage of the transistors without being unduly influenced by the further processing. For this purpose, it turns out that, for P-channel transistors, an appropriate adaptation of the band gap of the channel semiconductor material may be required in order to appropriately set the work function of the P-channel transistors. For this reason, frequently, a so-called threshold adjusting semiconductor material, for instance in the form of a silicon/germanium mixture, may be formed on the active regions of the P-channel transistors prior to forming the gate electrode structures, thereby obtaining the desired offset in the band gap of the channel semiconductor material. Although this concept is a promising approach for forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the adjustment of the transistor characteristics may be difficult to achieve on the basis of conventional strategies, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a silicon-based semiconductor layer 102. The semiconductor layer 102 comprises a plurality of “active” regions, such as semiconductor regions 102A, 102B, which are laterally delineated by an isolation structure (not shown), that may, for instance, by provided in the form of a shallow trench isolation. It should be appreciated that an active region, such as the semiconductor regions 102A, 102B, is to be understood as a semiconductor region in and above which one or more transistors are to be formed. For example, the active region 102A may be used for forming a transistor 150A, which, in the example shown, represents a P-channel transistor. Similarly, a transistor 150B is to be formed in and above the active region 102B and represents an N-channel transistor. Consequently, the basic doping in the active regions 102A, 102B is appropriately adapted to the different conductivity types of the transistors 150A, 150B. Furthermore, in the manufacturing stage shown, the transistor 150A comprises a gate electrode structure 160A, which may also be referred to as a high-k metal gate electrode structure, since it may comprise a gate dielectric material 161 having incorporated therein any high-k type material, for instance based on hafnium oxide, zirconium oxide and the like. It should be appreciated that the gate dielectric material 161 may further comprise a “conventional” dielectric material, such as silicon oxynitride and the like, so as to provide a superior interface characteristic, if required. Furthermore, the gate electrode structure 160A comprises a metal-containing material layer 162A, which may also have incorporated therein an appropriate metal species for adjusting the work function of the gate electrode structure 160A, as explained above. For this purpose, an aluminum species may be incorporated into the material 162A, which may basically be comprised of a titanium nitride material and the like. In other approaches, the work function species may be incorporated in the gate dielectric material 161, while the layer 162A may represent an appropriate electrode material, such as titanium nitride. Furthermore, a semiconductor-based electrode material 163, such as an amorphous silicon material, a polycrystalline silicon material and the like, is formed above the material 162A. Finally, the gate electrode structure 160A comprises a dielectric cap layer 164, such as a silicon nitride material and the like. As previously explained, in sophisticated semiconductor devices, a gate length, i.e., in FIG. 1a, the horizontal extension of the gate electrode structure 160A, may be 40 nm and less. Similarly, the transistor 150B comprises a gate electrode structure 160B, which may have a similar configuration as the gate electrode structure 160A in view of the gate dielectric material 161, the electrode material 163 and the cap layer 164. On the other hand, a conductive cap material 162B and/or the gate dielectric material 161 may have incorporated therein an appropriate work function metal species, such as a lanthanum species, in order to obtain a desired work function so as to adjust an appropriate threshold voltage for the transistor 150B.
As previously explained, it may be necessary to generate an appropriate band gap offset of the semiconductor material in the channel region 152 of one of the transistors 150A, 150B, which may be accomplished by providing an appropriately adapted semiconductor material, such as a silicon/germanium alloy 152A in the transistor 150A. Consequently, by appropriately selecting a thickness and a germanium concentration of the layer 152A, a desired bending of the band structure of the channel region 152 with respect to the gate electrode structure 160A may be achieved.
Furthermore, in the manufacturing stage shown, the sidewalls of the gate electrode structure 160A are masked by a protective spacer 103, such as a silicon nitride material, in combination with an oxide spacer material 104 and a further spacer element 105S, wherein these spacer elements may substantially define the lateral offset of a strain-inducing semiconductor material 151, such as a silicon/germanium material, from the channel region 152. As discussed above, the strain-inducing material 151 may enhance performance of the transistor 150A by inducing, for instance, a compressive strain component in the channel region 152. On the other hand, the gate electrode structure 160B and the active region 102B are covered by a spacer layer 105, while the spacer elements 103 and 104 are also formed on sidewalls of the gate electrode structure 160B.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of well-established process techniques for providing the active regions 102A, 102B by forming isolation structures and incorporating a desired well dopant species. Thereafter, the dielectric material 161 in combination with the materials 162A, 162B are provided, wherein appropriate patterning regimes may be applied so as to selectively provide the material 162A above the active region 102A and the material 162B above the active region 102B. In other process strategies, one of the materials 162A, 162B may also be provided in the other gate electrode structure, however, embedded in a diffusion blocking material so as to substantially not influence the work function of the gate electrode structure under consideration. Prior to or after providing the electrode material 163, additional heat treatments may be performed so as to diffuse the corresponding work function metal species into the layers 162A and 162B, respectively, and also towards the gate dielectric material 161. Furthermore, during the corresponding heat treatment, a thermal stabilization may be achieved, thereby reducing any effect of further heat treatment to be performed in later manufacturing stages.
In still other approaches, the work function adjusting species may be provided as material layers and may be diffused into the dielectric material 161, followed by the removal of these material layers and the deposition of the layers 162A, 162B, which may then have the same configuration in the gate electrode structures 160A, 160B.
Next, the resulting gate layer stack is patterned on the basis of sophisticated lithography and etch techniques, thereby obtaining the gate electrode structures 160A, 160B as shown in FIG. 1a. Consequently, the work function and thus the threshold voltages of the transistors 150A, 150B may be determined in an early manufacturing stage, thereby, however, requiring a reliable confinement of, in particular, the sensitive materials 161, 162A and 162B. For this purpose, a silicon nitride liner material is deposited, for instance, on the basis of highly conformal and uniform thermally activated and/or plasma activated chemical vapor deposition (CVD) techniques, in which a highly dense silicon nitride material may be provided with a highly controllable deposition rate and with very uniform material characteristics. The silicon nitride liner is then anisotropically etched in order to provide the protective spacer 103. In view of the superior integrity of the materials 161, 162A, 162B, an increased width of the spacer 103 is considered superior, while, on the other hand, in view of overall transistor performance, a reduced width would be preferable since the spacer 103 is to be maintained throughout the entire process flow and thus contributes to the total width of any additional spacers, which may determine the lateral offset of the material 151, the lateral offset of drain and source extension regions and halo regions and the like. In the example shown, the spacer 104 is provided in the form of a silicon dioxide material so as to preserve integrity of the spacer 103 in a later manufacturing stage, when the dielectric cap layer 164 is to be removed from the gate electrode structures 160A, 160B. Moreover, the spacer 105S may define the final lateral offset of the material 151 and may provide superior chemical stability in view of wet chemical etch recipes, which are typically to be applied for removing contaminants and the like, which, however, may remove silicon dioxide material. For this purpose, the spacer layer 105 is deposited as a silicon nitride material and is then selectively etched above the active region 102A in order to obtain the spacer element 105S, while the layer 105 is preserved above the active region 102B so as to act as a growth mask during the further processing of the device 100. Thereafter, an etch process is applied so as to form cavities in the active region 102A which are refilled with the material 151 based on a selective epitaxial growth technique. During this process, the semiconductor material 163 of the gate electrode structure 160A is covered by the dielectric cap material 164 and the spacers 103, 104, 105S, while the active region 102B and the gate electrode structure 160B are protected by the spacer layer 105. Thereafter, silicon nitride materials are removed on the basis of hot phosphoric acid. Consequently, the spacer layer 105, the spacer element 105S and the dielectric cap layers 164 are removed, while the offset spacer 104 may preserve integrity of the protective spacer 103. Next, the spacer 104 may be removed on the basis of hydrofluoric acid.
FIG. 1b schematically illustrates the semiconductor device 100 after the above-described process sequence. As illustrated, the semiconductor material 163 of the gate electrode structures 160A, 160B is exposed, while sidewalls of the gate electrode structures are still covered by the protective spacer 103.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a spacer structure 153, for instance in the form of a silicon nitride material, possibly in combination with an oxide liner (not shown), is formed on the protective spacer 103 in order to provide superior confinement of the sensitive materials 161, 162A, 162B, thereby also defining the lateral entry point for implantation species that may be incorporated during corresponding implantation sequences 106A, 106B. As also previously explained with reference to the protective spacer 103, the spacer structure 153 may also have a significant influence on the integrity of the sensitive gate electrode structures 160A, 160B, which may directly translate into corresponding production yield values. That is, an increased thickness of the spacer 153 may provide superior production yield, while at the same time the increased offset from the channel region 152 may result in a significant deterioration of transistor performance.
As previously discussed, during the implantation sequence 106A, the drain and source dopant species for forming extension regions 154 is introduced wherein the lateral offset of the extension regions 154 is determined by the spacer element 153. Furthermore, corresponding counter-doped regions 155, also referred to as halo regions, are formed during the implantation sequence 106A based on implantation energies so as to appropriately “embed” the drain and source extension regions 154 in the counter-doped regions 155. Similarly, the implantation sequence 106B may result in corresponding extension regions 154 and halo regions 155, wherein well-established masking regimes are to be applied which may involve a plurality of resist strip processes and cleaning processes, during which a superior encapsulation of the sensitive gate electrode structures 160A, 160B is advantageous.
FIG. 1d schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, a further spacer structure 156 is formed adjacent to the spacer 153, thereby defining a lateral offset of drain and source regions 157, which are formed for the different transistors 150A, 150B on the basis of an appropriate masking regime after providing the spacers 156 on the basis of well-established process techniques. Thereafter, an anneal sequence 107 is performed so as to activate the dopants in the extension regions 154 and the drain and source regions 157, thereby also re-crystallizing implantation-induced damage. Furthermore, during the anneal sequence 107, a desired overlap of the extension regions 154 with the gate electrode structures 160A, 160B is to be generated in order to obtain a desired Miller capacitance, as discussed above. When providing a superior encapsulation for the gate electrode structures 160A, 160B, for instance in view of increasing production yield, however, the extension regions 154 may not be appropriately “driven” into the channel regions 152. For this purpose, typically, the implantation dose of the implantation sequences 106A, 106B of FIG. 2c is appropriately increased to provide a higher dopant concentration and thus an increased overlap of the extension regions 154. However, the implantation dose may not be arbitrarily increased due to throughput-related issues. That is, for given implantation resources in the production facility a further increase in implantation dose may result in a significantly reduced overall throughput. In P-channel transistors, such as the transistor 150A, having implemented therein the threshold adjusting semiconductor material 152A, the situation may become even more complex, as discussed above, since the diffusivity of the P-type dopant species, such as boron, is significantly reduced in a silicon/germanium material, thereby further reducing the degree of overlap obtained on the basis of a given dopant concentration and process parameters of the anneal sequence 107. On the other hand, increasing anneal temperatures may be less than desirable since the dopant species of the drain and source regions 157 may increasingly diffuse into the well region, thereby reducing the distance between the drain and source regions. Furthermore, upon using increased anneal temperatures, dopant species may increasingly diffuse into the channel region and may result in an increased depth of the junction profile, which may in turn translate into higher leakage currents and increased strain-induced barrier lowering. Furthermore, the increased dopant concentration near the channel region may result in a higher probability of punch through events. Moreover, in the drain and source regions, a desired high dopant concentration is to be maintained in view of forming a metal silicide material, such as a nickel silicide, which forms a Schottky barrier with the semiconductor material, wherein the barrier may be significantly lowered upon providing a high dopant concentration. Similarly, the semiconductor material in the gate electrode structure requires a high dopant concentration in order to also lower the Schottky barrier therein.
Consequently, as indicated by experiments, a superior encapsulation of the high-k metal gate electrode structures, which may result in a significant increase of production yield, may result in a corresponding loss of performance, for instance up to 12 percent for P-channel transistors and up to 8 percent in N-channel transistors have been determined due to a corresponding reduction of the Miller capacitance caused by a desirable encapsulation of the gate electrode structures.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.